1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, particularly an FET (Field Effect Transistor) of the MIS (Metal Insulator Semiconductor) type, and to a method for forming a silicon-containing dielectric (insulating) film, utilized in, e.g., a semiconductor processing system. The term “semiconductor process” used herein includes various kinds of processes which are performed to manufacture a semiconductor device or a structure having wiring layers, electrodes, and the like to be connected to a semiconductor device, on a target substrate, such as a semiconductor wafer or a glass substrate used for an LCD (Liquid Crystal Display) or FPD (Flat Panel Display), by forming semiconductor layers, insulating layers, and conductive layers in predetermined patterns on the target substrate.
2. Description of the Related Art
In recent years, owing to the demands of increased miniaturization, CMOS (Complementary Metal Oxide Semiconductor) transistors comprising MISFETs having a dual metal gate structure have attracted attentions. For example, Samavedam et al., IEDM Tech. Digest, p. 443, 2002 (Non-Patent Document 1) discloses a process for manufacturing a CMOS transistor, as shown in FIGS. 27 to 31.
At first, as shown in FIG. 27, an n-type well 102 and a p-type well 103 are respectively formed in the surface of first and second areas 101A and 101B of a silicon substrate 101. Then, as shown in FIG. 28, an HfO2 film 104 to be used as a gate dielectric (insulating) film, a TiN film 105 to be used as a first gate electrode material, and a silicon oxide film 106 to be used as an etching mask material are deposited in this order on the substrate 101. Then, a photo-resist mask 107 is formed on the silicon oxide film 106 by utilizing the mask for the p-type well. Then, as shown in FIG. 29, the part of the silicon oxide film 106 within the second area 101B is removed to form a hard mask 106a made from the silicon oxide film and covering the first area 101A. Then, as shown in FIG. 30, the exposed portion of the TiN film is removed by wet etching using the hard mask 106a. Then, after the hard mask 106a is removed by HF (hydrogen fluoride), as shown in FIG. 31, a TaSiN film 108 to be used as a second gate electrode material and a poly-crystalline silicon film 109 are deposited in this order all over the substrate. The hard mask may be formed of a silicon nitride film.
Thereafter, although not disclosed in Non-Patent Document 1, ordinary steps are conducted to perform gate electrode patterning, and formation of extensions (which are to be used as lightly doped regions in source/drain layers), gate sidewalls, source/drain layers, and interconnections, thereby completing a complementary transistor structure of the MIS type.